The present invention relates to a method for manufacturing a semiconductor device, and relates in particular to a method for manufacturing a semiconductor device whereby a smaller mounting area can be provided by reducing the external size of a package without using lead forming, and a considerable reduction in manufacturing costs can be realized.
In a process for the manufacture of semiconductor devices, multiple semiconductor chips, produced from a single wafer by dicing, are securely mounted in a lead frame, after which transfer molding, using a die and resin injection, is used to seal them. The thus sealed semiconductor chips are then separated to provide multiple individual semiconductor devices. For this process, either a strip-shaped or a hoop-shaped lead frame is employed, but regardless of which type of lead frame is used, only a single sealing procedure is required to simultaneously seal a plurality of semiconductor devices.
FIG. 15 is a diagram showing the process for checking semiconductor chips formed on a wafer. During this process, the quality of each semiconductor chip 1 formed on a wafer 15 is determined. First, the position of the wafer is recognized, and a needle 14 of a probe is fed a distance equivalent to the chip size and is brought into contact with the electrode pad of a semiconductor chip 1. In this state, an input signal wave, which is programmed in advance, is received from an electrode pad, and the output terminal emits a constant signal wave. A tester reads this signal and determines the quality of the semiconductor chip 1. And when the semiconductor chip 1 is determined to be defective, a mark is provided for it, so that when a recognition camera identifies this mark during the process performed to bond the semiconductor chip 1 to the lead frame, the defective semiconductor chip 1 can be removed.
FIG. 16 is a diagram showing a transfer molding process. During this process, the semiconductor chip 1 fixed to a die pad of a lead frame 2 by die bonding or wire bonding is mounted inside a cavity 4, formed of an upper and a lower die 3A and 3B, and an epoxy resin is injected into the cavity 4 to seal the semiconductor chip 1. Once the process has been completed, the lead frame 2 is cut to complete the fabrication of a separate semiconductor device (e.g., Japanese Patent Publication No. H05-129473).
For this process, as is shown in FIG. 17, multiple cavities 4a to 4f, a resin source 5 for injecting a resin, a runner 6, and gates 7 for injecting the resin into the cavities 4a to 4f via the runner 6, are formed in the surface of the die 3B. For example, if ten semiconductor chips 1 are mounted on a single lead frame, ten cavities 4, ten gates 7 and one runner 6 are formed for one lead frame. And the cavities 4 equivalent to, for example, twenty lead frames are formed in the inner surfaces of the die 3.
FIG. 18 is a diagram showing a semiconductor device obtained by transfer molding. The semi conductor chip 1 whereon elements, such as transistors, are formed is securely attached to an island 8 of the lead frame by a brazing material 9, such as solder; the electrode pad of the semiconductor chip 1 is connected to a lead terminal 10 by a wire 11; the periphery of the semiconductor chip 1 is covered with a resin 12 that conforms to the shapes of the cavities 4; and the distal end of the lead terminal 10 is extended outside the resin 12.
Following this, according to the above manufacturing method, the semiconductor chips 1 formed on the wafer are separated into semiconductor devices, and the electrical characteristics (hfe ranks) of these semiconductor devices are measured and determined by a tester. At this time, a check is conducted in accordance with the items that could not be correctly measured during the wafer checking process in the wafer state as is explained while referring to FIG. 15, and/or with the stricter measurement of items referring to the product standards. During the process for measuring and determining the electrical characteristic of a semiconductor device, all the semiconductor devices are aligned in a predetermined direction, and are checked, one by one. Following this process, the semiconductor devices that are determined to be excellent are taped and shipped.
According to the conventional method for manufacturing semiconductor devices using transfer molding, since following the transfer molding the semiconductor chips are cut off and separated into individual semiconductor devices, the electrical characteristics (hfe ranks) are measured for those semiconductor devices that are aligned in a predetermined direction. Thereafter, the semiconductor devices are sorted and taped in accordance with the measured characteristics, so that extra time and processing are required.
Further, when semiconductor devices, the electrical properties of which are determined during processing performed to measure and determine their characteristics, are taped without being sorted in accordance with the hfe ranks, a plurality of taping lines must be prepared. Therefore, since a taping device can not be structured simply, extra working space is required and a limit is imposed on the determinations that can be performed to assign excellent semiconductor devices to multiple ranks.
To achieve the shortcomings, according to the invention, a method for manufacturing a semiconductor device comprises the steps of:
bonding one semiconductor chip to each of multiple mounting portions of a substrate;
covering the semiconductor chips bonded to the mounting portions with a common resin layer;
bringing the substrate into contact with the resin layer and gluing the substrate to a adhesive sheet;
performing dicing and measurement for the semiconductor chips that are glued to the adhesive sheet. Thus, the semiconductor chips that are integrally supported by the adhesive sheet can be measured, without the having to be separated into individual semiconductor devices.
Further, according to the invention, a method for manufacturing a semiconductor device comprises the steps of:
bonding a semiconductor chip to each of multiple mounting portions of a substrate;
covering the semiconductor chips bonded to the mounting portions with a common resin layer;
bringing the substrate into contact with the resin layer and gluing the substrate to an adhesive sheet;
dicing and measuring the semiconductor chips while the substrate is glued to the adhesive sheet; and
storing directly in a carrier tape semiconductor devices glued to the adhesive sheet. Thus, the semiconductor chips can be processed while integrally supported by the adhesive sheet, and need not be separated into individual semiconductor devices until they are stored in a carrier tape.
Furthermore, not only whether the electrical property of each semiconductor device is excellent or inferior, but also the rank to which an excellent semiconductor device belongs can be determined. Additionally, for all the semiconductor devices formed on a substrate, the position and the level of the electrical characteristic are stored as data, and semiconductor devices having the required electrical taping characteristics are selectively collected and taped.